Planarization process, apparatus and method of manufacturing an article

ABSTRACT

A planarization apparatus comprising a superstrate chuck is provided. The superstrate includes a plurality of inner lands protruding from a surface of the superstrate chuck and a peripheral land protruding from the surface of the superstrate chuck along a periphery of the superstrate chuck and encircling the inner lands therein. The peripheral land has a height smaller than a height of each of the inner lands. The peripheral land has a width sufficiently larger than a width of each of the inner lands such that a pressure leakage through the peripheral land is controlled to be less than a threshold.

BACKGROUND Field of Art

The present disclosure relates to substrate processing, and moreparticularly, to the nanoimprint lithography or planarization ofsurfaces in semiconductor fabrication.

Description of the Related Art

Imprint and planarization techniques are useful in fabricatingsemiconductor devices. For example, the process for creating asemiconductor device includes repeatedly adding and removing material toand from a substrate. This process can produce a layered substrate withan irregular height variation (i.e., topography), and as more layers areadded, the substrate height variation can increase. The height variationhas a negative impact on the ability to add further layers to thelayered substrate. Separately, semiconductor substrates (e.g., siliconwafers) themselves are not always perfectly flat and may include aninitial surface height variation (i.e., topography). One method ofaddressing this issue is to planarize the substrate between layeringsteps. Various lithographic patterning methods benefit from patterningon a planar surface. In ArF laser-based lithography, planarizationimproves depth of focus (DOF), critical dimension (CD), and criticaldimension uniformity. In extreme ultraviolet lithography (EUV),planarization improves feature placement and DOF. In nanoimprintlithography (NIL) planarization improves feature filling and CD controlafter pattern transfer.

A planarization technique sometimes referred to as inkjet-based adaptiveplanarization (IAP) involves dispensing a variable drop pattern ofpolymerizable material between the substrate and a superstrate, wherethe drop pattern varies depending on the substrate topography. Asuperstrate is then brought into contact with the polymerizable materialafter which the material is polymerized on the substrate, and thesuperstrate removed. Improvements in nanoimprint lithography andplanarization techniques, including IAP techniques, are desired forimproving, e.g., whole wafer processing, step and repeat processing, andsemiconductor device fabrication.

SUMMARY

A planarization or imprint system including at least a superstrate and asubstrate sandwiching a formable material therebetween is provided. Thesuperstrate having a first side in contact with the formable materialand a second side opposite to the first side. A first conductive portionis provided at the second side of the superstrate. The substrateincludes at least a second conductive portion. Both the first conductiveportion and the second conductive portion are grounded during aseparation process to separate the superstrate from the substrate. Thefirst conductive portion may include a transparent conductive layerformed on the second side of the superstrate before an imprint processperformed on the formable material. The first conductive portion may beplaced at the second side of the superstrate after a UV exposure hasbeen performed on the formable material. The first conductive layer mayalso include a conductive superstrate chuck to retain the superstrateduring an imprint process. The first conductive portion may be made ofchromium (Cr), tin nitride (TiN), or tin oxide (SnO₂). The firstconductive portion may be in the form of a film, a sheet, or a wire meshmade for example from stainless steel, aluminum or other conductivematerial. In one embodiment, the first conduct layer has a thickness ofabout 10 nm to about 15 nm.

The second conductive portion may include the substrate made ofconductive material. The second conductive portion may alternativelyinclude a conductive layer formed on the substrate. The secondconductive portion may also include a conductive substrate chuck such asspecially prepared non-stoichiometric silicon carbide (SiC) retainingthe substrate during an imprint process.

A method is provided, including curing a formable material sandwichedbetween a superstrate and a substrate and separating superstrate and thesubstrate with the following steps. A back side of the superstrate isground, wherein the back side is opposite to a front side of thesuperstrate in contact with the formable material. The bottom side ofsubstrate that is in contact to the wafer chuck is grounded. Separatingthe superstrate away from the substrate, or moving the substrate awayfrom the superstrate, in a vertical direction while both the back sideof the superstrate and the substrate are grounded and until an electricfield between the superstrate and the cured formable material is below apredetermined value. The superstrate and the substrate are moved furtheraway from each other in a lateral direction in order, for example, tounload substrate or superstrate, or both. A surface discharging isperformed while moving the superstrate with respect to the substrate (ormoving the substrate with respect to the superstrate) in the lateraldirection.

A method of reducing static electric fields during a separation processfor separating a superstrate from a substrate is provided. A secondcapacitor is introduced between back side of the superstrate, and frontsurface of superstrate, wherein the back side is opposite to a frontside in contact with a resist sandwiched between the superstrate and thesubstrate. A third capacitor is introduced between the top side offormable material which is in contact with superstrate and groundedsurface of substrate. The ground is connected with both the secondcapacitor and the third capacitor to form a close loop of electriccurrent comprising the second capacitor, third capacitor and a firstcapacitor formed between the first side of superstrate and top side offormable material during a separation process, and the second capacitorconnected in series. The method may further comprise separating thesuperstrate from the substrate in a vertical direction in the separationprocess until the superstrate and the substrate is completely separatedand an electric field between the superstrate and the substrate isreduced to a predetermined value; and moving the superstrate in alateral direction with respect to the substrate (or moving the substratein the lateral direction with respect to the superstrate). A surfacedischarge process may be performed before moving the superstrate in thelateral direction with respect to the substrate. The second capacitormay be introduced by providing a conductive layer at the back side ofthe superstrate and an electric connection between the conductive layerand the ground. The conductive layer may be formed with transparentmaterial on the back side superstrate before performing an imprintprocess. The conductive layer may be formed on the back side of thesuperstrate after a UV exposure has been performed. The second capacitormay be introduced by providing a conductive superstrate chuck to retainthe superstrate during the separation process and an electric connectionbetween the conductive superstrate chuck and the ground. The thirdcapacitor may be introduced by providing the substrate made ofconductive material and an electric connection between the substrate andthe ground. The first capacitor may also be introduced by providing aconductive substrate chuck to retain the superstrate during theseparation process and an electric connection between the conductivesubstrate chuck and the ground.

These and other objects, features, and advantages of the presentdisclosure will become apparent upon reading the following detaileddescription of exemplary embodiments of the present disclosure, whentaken in conjunction with the appended drawings, and provided claims.

BRIEF DESCRIPTION OF DRAWINGS

So that features and advantages of the present invention can beunderstood in detail, a more particular description of embodiments ofthe invention may be had by reference to the embodiments illustrated inthe appended drawings. It is to be noted, however, that the appendeddrawings only illustrate typical embodiments of the invention and aretherefore not to be considered limiting of its scope, for the inventionmay admit to other equally effective embodiments.

FIG. 1 is a diagram illustrating a planarization and/or an imprintsystem;

FIG. 2A to 2C illustrates a planarization and/or imprint process;

FIGS. 3A to 3C show the superstrate and the substrate of the imprintsystem during the initial separation process;

FIG. 4 shows the superstrate and the substrate of the imprint systemduring a lateral separation process of the imprint process;

FIG. 5 shows the conductive structures formed at both the superstrateand the substrate according to one embodiment;

FIG. 6A show the initial separation of the substrate and the superstratein a vertical direction without grounding; and FIG. 6B the sameseparation process with grounding

FIGS. 7A and 7B shows various stages of lateral separation of thesuperstrate with respect to the substrate; and various stages ofelectric field distribution

FIG. 8 shows the electric charge distribution when the substrate isconductive but includes an insulating film on both sides of thesubstrate;

FIG. 9 shows the surface charges removal by electrically grounded iondischarge sources;

FIG. 10 shows an equivalent electric capacitor corresponding to asandwich of a superstrate, a formable material, and a substrate;

FIG. 11 shows an equivalent electric circuit of the structure as shownin FIG. 6B;

FIGS. 12A and 12B show the results of partial and complete lateralseparation of the superstrate and the substrate as shown in FIG. 7A andFIG. 7B;

FIG. 13 shows the graph of the electric field strength as a function ofvertical distance for different layers;

FIG. 14 shows the graph of the electric field strength as a function ofvertical distance when the substrate and the substrate are consideredconductive; and

FIG. 15 shows the method of minimizing the electric field between thesuperstrate and the substrate caused by separation after the curingprocess.

Throughout the figures, the same reference numerals and characters,unless otherwise stated, are used to denote like features, elements,components or portions of the illustrated embodiments. Moreover, whilethe subject disclosure will now be described in detail with reference tothe figures, it is done so in connection with the illustrative exemplaryembodiments. It is intended that changes and modifications can be madeto the described exemplary embodiments without departing from the truescope and spirit of the subject disclosure as defined by the appendedclaims.

DETAILED DESCRIPTION Planarization System

FIG. 1 illustrates a nanoimprint and/or planarization system 10 in whichan embodiment may be implemented. The system 10 may be used to planarizethe substrate 12 or form a relief pattern on substrate 12. Substrate 12may be coupled to substrate chuck 14. As illustrated, substrate chuck 14is a vacuum chuck. Substrate chuck 14, however, may be any chuckincluding, but not limited to, vacuum, pin-type, groove-type,electrostatic, electromagnetic, and/or the like.

The substrate 12 and the substrate chuck 14 may be further supported bypositioning stage 16. The stage 16 may provide translational and/orrotational motion along one or more of the x, y, z, θ, and ϕ axes. Thestage 16, the substrate 12, and the substrate chuck 14 may also bepositioned on a base (not shown).

Spaced-apart from the substrate 12 is a superstrate 18 used to planarizethe substrate. The superstrate is a flat planar member. In analternative embodiment the superstrate 18 is a template 18. The template18 may include a body having a first side and a second side with oneside having a mesa (also referred to as mold) extending therefromtowards the substrate 12. The mesa may have a shaping surface 22thereon. Alternatively, the template 18 may be formed without a mesa.

The template 18, that is, the superstrate 18, and/or the mold may beformed from such materials including, but not limited to, fused-silica,quartz, silicon, organic polymers, siloxane polymers, borosilicateglass, fluorocarbon polymers, metal, hardened sapphire, and/or the like.As illustrated, shaping surface 22 may be a planar surface or maycomprise features defined by a plurality of spaced-apart recesses and/orprotrusions, though embodiments of the present invention are not limitedto such configurations. The shaping surface 22 may define any originalpattern that forms the basis of a pattern to be formed on the substrate12. The shaping surface 22 may be blank, i.e. without pattern features,in which case a planar surface can be formed on the substrate 12. In analternative embodiment, when the shaping surface 22 is of the same arealsize as the substrate, a layer can be formed over the entire substrate(e.g., whole substrate processing). In an alternative embodiment, whenthe shaping surface 22 is smaller than the substrate, a layer can beformed over a portion of the substrate one at a time which is thenrepeated to cover the entire substrate (e.g., step and repeatprocessing).

The superstrate 18 (template 18) may be coupled to a superstrate chuck28 (template chuck 28). The superstrate chuck 28 may be configured as,but not limited to, vacuum, pin-type, groove-type, electrostatic,electromagnetic, and/or other similar chuck types. Further, thesuperstrate chuck 28 may be coupled to a head 30 which in turn may bemoveably coupled to a bridge 36 such that superstrate chuck 28, the head30 and the template 18 are moveable in at least the z-axis direction.

The system 10 may further comprise a fluid dispense system 32. Fluiddispense system 32 may be used to deposit a formable material 34 (e.g.,polymerizable material) on substrate 12. The formable material 34 may bepositioned upon the substrate 12 using techniques such as drop dispense,spin-coating, dip coating, chemical vapor deposition (CVD), physicalvapor deposition (PVD), thin film deposition, thick film deposition,and/or the like. The formable material 34 may be disposed upon thesubstrate 12 before and/or after a desired volume is defined between thesuperstrate 18 (mold) and the substrate 12 depending on designconsiderations.

The fluid dispense system 32 may use different technologies to dispensethe formable material 34. When the formable material 34 is capable ofjetting, ink jet type dispensers may be used to dispense the formablematerial. For example, thermal ink jetting, microelectromechanicalsystems (MEMS) based ink jetting, valve jet, and piezoelectric inkjetting are common techniques for dispensing jettable liquids.

The system 10 may further comprise radiation source 38 that directsactinic energy along a path 42. The head 30 and the stage 16 may beconfigured to position the template 18 and the substrate 12 insuperimposition with the path 42. A camera 58 may likewise be positionedin superimposition with the path 42. The system 10 may be regulated by aprocessor 54 in communication with the stage 16, the head 30, the fluiddispense system 32, the source 38, and/or the camera 58 and may operateon a computer readable program stored in a memory 56.

Either the head 30, the stage 16, or both vary a distance between thesuperstrate 18 (mold) and the substrate 12 to define a desired volumetherebetween that is filled by the formable material 34. For example,head 30 may apply a force to template 18 such that the mold contacts theformable material 34. After the desired volume is filled with theformable material 34, the source 38 produces actinic energy (e.g.,ultraviolet radiation) causing the formable material 34 to solidifyand/or cross-link conforming to a shape of a surface 44 of the substrate12 and the surface 22 of the template 18, defining a formed layer on thesubstrate 12.

Planarization Process

The planarization process and nanoimprint process include steps whichare shown schematically in FIGS. 2A to FIG. 2C which may make use of theplanarization or the nanoimprint system 10 configured to perform theplanarization process or nanoimprint process. As illustrated in FIG. 2A,the formable material 34 in the form of droplets is dispensed onto thesubstrate 12. As discussed previously, the substrate surface has sometopography which may be known based on previous processing operations ormay be measured using a profilometer, AFM, SEM, or an optical surfaceprofiler based on optical interference effect like Zygo NewView 8200.The local volume density of the deposited formable material 34 is varieddepending on the substrate topography and/or the template topography.The superstrate 18 is then positioned in contact with the formablematerial 34. As used herein, template and superstrate are usedinterchangeably to describe an object with a shaping surface 22 that isbrought into contact with the formable material 34 to control the shapeof the formable material 34. As used herein, template chuck 28 andsuperstrate chuck 28 are used interchangeably to hold the template 18 orthe superstrate 18.

FIG. 2B illustrates a post-contact step after the superstrate 18 hasbeen brought into full contact with the formable material 34 but beforea polymerization process starts. The superstrate 18 is equivalent to thetemplate 18 in FIG. 1 and is substantially featureless (may includealignment or identification features) and may be substantially the samesize and shape as the substrate (a characteristic dimension such asaverage diameter of the superstrate 18 may be within at least 3% of acharacteristic dimension of the substrate 12). In an alternativeembodiment, the superstrate 18 is a template 18 may be smaller than thesubstrate and may have a shaping surface 22 with features that used toform features in the cured layer 34″. As the superstrate 18 contacts theformable material 34, the droplets merge to form a formable materialfilm 34′ that fills the space between the superstrate 18 and thesubstrate 12. Preferably, the filling process happens in a uniformmanner without any air or gas bubbles being trapped between thesuperstrate 18 and the substrate 12 in order to minimize non-filldefects. The polymerization process or curing of the formable material34 may be initiated with actinic radiation (e.g., UV radiation). Forexample, radiation source 38 of FIG. 1 can provide the actinic radiationcausing formable material film 34′ to cure, solidify, and/or cross-link,defining a cured planarized layer 34″ or a cured layer 34″ which mayinclude features on the substrate 12. Alternatively, curing of theformable material film 34′ can also be initiated by using heat,pressure, chemical reaction, other types of radiation, or anycombination of these. Once cured, the cured layer (planarized layer) 34″is formed, the superstrate 18 can be separated therefrom. FIG. 2Cillustrates the cured (planarized) layer 34″ on the substrate 12 afterseparation of the superstrate 18.

Separation Process

After curing, the superstrate 18 (or template 18) and the planarizedlayer 34″ (or cured layer 34″) are separated from each other. As is wellunderstood, electric charges may be generated when two dissimilarmaterials are brought into contact and separated from each other. Forexample, this happens when a film of a first material is formed on asurface of a second material. Each of the first and second materials mayacquire a net electric charges of the same magnitude with a signopposite to each other. The charge separation may also be observed in atriboelectric effect due to friction between two materials. The chargeseparation happens due to a difference of work functions of the twodissimilar materials. The charge separation may also happen to twosurfaces of the same materials having different work functions in theareas with different physical or chemical conditions such as mechanicalstress or dopant concentrations. FIG. 3A shows a superstrate 18 broughtinto contact with a formable material 34, where the superstrate 18 andthe cured layer 34″ are formed of different materials. As shown in FIG.3B, the charge separation happens even when two materials, that is, thesuperstrate 18 and the cured layer 34″, are in a static contact. Onlyone interface between 18 and 34 is considered in the current embodiment.The signs of the charges depend on the materials of the contactsurfaces. In one embodiment, the charges 51 are positive and the charges52 are negative while the superstrate 18 formed of a glass material andthe cured layer 34″ is formed of a polymerized material for example aphotoresist, a planarization material, nanoimprint material, or otherresist. In some situations, the charges 51 may be negative and thecharges 52 may be positive, depending on the materials of thesuperstrate 18 and the cured layer 34″. As the charges 51 and 52 havethe same magnitude (absolute value), the electric fields generated bythe positive charges 51 and the negative charges 52 compensate eachother to produce zero electric field outside of an interface. This issimilar to a charged planar capacitor where the electric field outsideof the capacitor is zero.

The electric charges generated and accumulated on two surfaces ofdissimilar materials may partially survive a quick separation of thesetwo materials. The charge dynamics strongly depends on the nature of thematerials and the dynamics of the separation. During separation, most ofthe electric charges dissipate through a discharge process that includessurface conductance along the separation interface, and electrostaticdischarge through the gap filled with air or gas. The final level of theelectric charge value is established by lowest ionization threshold ofair or gas filling the space. The charges may reduce to levels thatcannot be easily dissipated through the known mechanisms. The remainingelectric charges may form high electric field and attract dust particleswhich may contain different materials such as organic, dielectric,semiconductor, conductive, oxide, metal or other particles. Theseparticles may steadily accumulate on the imprint and planarization toolsurfaces over time. Laminar flow of air inside the imprint andplanarization tools may keep the particles down. However, the electricfield may stir the particles to move, jump, or to be attracted to theelectrically charged working surfaces of the superstrate and thesubstrate.

FIG. 3C shows the separation performed by moving the superstrate 18 awayfrom the substrate 12, or by moving the substrate 12 away from thesuperstrate 18. The separation may generate electric field

in the gap between the superstrate 18 and the formable material layer34″ (the substrate 12) due to the electric charges 51 and 52. Theseparation may create electrostatic charges on the contact surfaces ofthe superstrate 18 and the formable material film 34″. When the spatialseparation is insignificant, the electric field

is contained inside the gap between the superstrate 18 and formablematerial 34. The superstrate 18 and formable material 34 act similarlyto an ideal flat capacitor where electric field exists only in the gapbetween the electrodes. As the electric field is zero or near zero nearthe edges, no particles outside of the gap will be attracted.

As the spatial separation increases, the non-compensated electriccharges may create macroscopic electric fields outside of thesuperstrate 18 and formable material 34 at a distance comparable to theseparation gap. For example, as show in FIG. 4 , the further separationbetween the superstrate 18 and the substrate 12 along a lateraldirection causes creation of electric fields

,

,

, and

due to the electric charges 51A and 52A. The electric charges are notcompensating each other like the case of the flat capacitor as shown inFIG. 3C, but produce macroscopic electric fields. Experimental evidenceshows that the electric fields may easily exceed 1×10⁶ V/m. Asunderstood, for comparison dielectric strength of dry air is within therange of about 1.5×10⁶ V/m to about 3×10⁶ V/m. The dielectric strengthdefines the electric field threshold at or above which plasma dischargestarts. During separation of the superstrate and the substrate,including the initial vertical separation and then the further lateralseparation, an electric discharge in air or other gas is possible. Ifthe value of the electric field is less than the dielectric strength,the electric charges are stable. The stable charges, non-compensatedelectric fields may cause problems with the particle control in theimprint equipment 10. Most of the dust particles are electricallycharged due to electrification by friction. Electric fields may move anddirectly attract or repel the electrically charged particles to thecharged superstrate and substrate. In addition, pondermotive forces maypush charged particles from regions of high electric fields towardsregions of lower electric fields to thereby stir the particles in air.

To resolve the issues of the displaced charged particles attracted tothe electrically charged surfaces of the superstrate and the substrate,an electrically conductive surface may be placed or formed nearseparation surfaces of the superstrate and the substrate. FIG. 5 showsan embodiment that incorporates conductive structures near thesuperstrate and the substrate. As shown, a conductive layer 53 may beplaced on top of the superstrate 18 opposite the shaping surface 22, andan electrically conductive chuck 14 is used to support the substrate 12.The conductive layer 53 may include a conductive film formed on the backside of the superstrate 18. For example, the conductive film may be ametal film (chromium, Cr) or a conductive film of titanium nitride (TiN)or tin oxide (SnO) formed by vapor or chemical deposition, a metalplate, a metal mesh or other structure. The thickness of the conductivelayer 53 may range between 10 nm and 15 nm. The conductive layer 53 maybe temporarily or permanently placed at the back side of the superstrate18 and removed during UV exposure. The conductive layer 53 may be formedof transparent conductive material and either temporarily or permanentlyplaced at the backside of the superstrate 18. The electricallyconductive substrate chuck 14 may also in the form of an intermediateelectrically conductive layer 64 that may be formed between thesubstrate 12 and the substrate chuck 14.

In FIG. 6A, initial separation between the superstrate 18 and the curedlayer 34″ on the substrate 12 along the vertical direction is performed.As shown, electric charges 51 and 52 are generated and an electric field

exists between the superstrate 18 and the cured layer 34″. As shown inFIG. 6A, the conductive structures may be connected to ground viaelectric paths 61 and 62, respectively. Each of the electric paths 61and 62 may include a switch S1 and S2 to open or close the connectionbetween the conductive structures 53 and 64 to ground, respectively.Alternatively, the electric connections between the ground andconductive structures 53 and 64 may be permanent without using theswitches S1 and S2. Before grounding the conductive structures 53 and64, for example, before closing the switches S1 and S2, an electricfield

is established between the superstrate 18 and formable material 34.

FIG. 6B shows the effect of grounding the conductive structures 53 and64 with closing the switches S₁ and S₂. Again, other electric paths suchas conductive wires may also be used to connect the conductivestructures 53 and 64 without the use of the switches S₁ and S₂. Thegrounding of the conductive structure 53 leads to the appearance ofcharges 55 at the backside of the superstrate 18, while the grounding ofthe conductive structure 64 leads the appearance of the charges 60 atthe surface of the substrate chuck 14 due to charge redistribution. Thesubstrate 12 may be considered as a non-conductive dielectric or asemi-conductive silicon wafer. The addition electric charges create theelectric fields

across the superstrate 18 and

across the substrate 12 in addition to the electric field

, respectively.

FIGS. 7A to 7B shows various stages of the lateral separation of thesuperstrate 18 with respect to the substrate 12. In the intermediatestage as shown in FIG. 7A, the electric field

exists in the overlapped area of the charges 51 and 52, while theelectric field is zero or near zero outside the overlapped area. FIG. 7Bshows the positions of the superstrate 18 and the substrate 12 when thelateral separation is complete and the charges 51 and 52 no longeroverlap with each other. The electric field between the charges 51 and52 is zero or near zero as there is no overlap between these charges.The charges 51 and 55 of the opposite signs at the superstrate 18 maycompensate each other, the electric field across the superstrate 18 iszero or near zero. Similarly, the charges 52 and 56 may compensate eachother, such that the electric across the substrate 12 is zero or nearzero.

In the embodiment as shown in FIG. 7B, the non-conductive substrate 12is used for simplification. In real application, the substrate 12 may beconductive by different levels of doping. However, the substrate 12often includes insulating film such as native silicon oxide Si₂O. FIG. 8shows the electric field distribution when the substrate 12 isconductive but includes an insulating film similar to SiO₂ on thesurface of the substrate 12. As shown, charges 57 and 67 are formedinside of the conductive substrate 12. The additional layer of electriccharges (double charge layers) does not change the general approach asdescribed with reference to FIGS. 7A and 7B.

In FIG. 9 , electrically grounded ion discharge sources 63 and 64, forexample, alpha ionizers, X-rays, or other ionizing bars, may be placednear the surfaces of the substrate 12 and the superstrate 18 to removethe surface charges 51 and 52 after the lateral separation is complete.

FIG. 10 shows an electrically equivalent capacitor scheme correspondingto the sandwich of the superstrate 18, the formable material 34″, andthe substrate 12. Q_(i), C_(i), and V_(i) are the initial charges,initial capacitance, and initial voltage between the superstrate 18 andthe formable material 34″ at the initial separation. The initial chargesQ_(i) remain stable after the initial separation and plasma discharge.FIG. 11 shows an equivalent circuit of the structure as shown in FIG.6B. As shown, by grounding the conductive structures 53 and 54, a closedloop of electric circuit is formed. The electric circuit includescapacitors C₀, C₁, and C₂ connected in series. The initial charges Q_(i)is redistributed across the three capacitors C₀, C₁, and C₂. As thecapacitors C₁ and C₂ are charged with the same electric current,

|Q₁|=|Q₂|  (0), and

|Q ₁ |=|Q ₂ |−|Q ₁|  (1).

On the other hand, the voltages on the capacitors are related as:

V ₀ +V ₁ =V ₂   (2).

The definition of a capacitor formula for each combination of theelectric charge, voltage, and capacitance value can be used, forexample,

Q₀=C₀V₀   (3).

The equation (2) can then be rewritten as:

$\begin{matrix}{\frac{Q_{0}}{C_{0}} = {\frac{Q_{1}}{C_{1}} + {\frac{Q_{2}}{C_{2}}.}}} & (4)\end{matrix}$

Based on the above equations, the following relationships can beobtained:

$\begin{matrix}{{Q_{0} = {Q_{i}\frac{C_{1} + C_{2}}{C_{1} + C_{2} + \frac{C_{1}C_{2}}{C_{0}}}}};} & (5)\end{matrix}$ $\begin{matrix}{{{Q_{1}}_{`} = {Q_{i}\frac{1}{1 + \frac{C_{0}}{C_{1}} + \frac{C_{0}}{C_{2}}}}};} & (6)\end{matrix}$ $\begin{matrix}{{V_{1} = \frac{Q_{1}}{C_{1}}};{and}} & (7)\end{matrix}$ $\begin{matrix}{V_{2} = {V_{1}{\frac{C_{1}}{C_{2}}.}}} & (8)\end{matrix}$

A typical value for the electric field measured by an electrostaticvoltmeter after initial separation as shown in FIG. 3C is around 10⁶V/m. This value is close to the electric discharge value in dry air inthe range of 1.5×10⁶ V/m to 3×10⁶ V/m. Higher electric fields wouldcause electric discharge in air or gas until the value of electric fieldfalls below the value necessary for self-supported plasma discharge. Theinitial separation distance between the superstrate and the substrate ina typical imprint/planarization tool may be around 10 μm. Let's considerthe substrate (wafer) and superstrate with a diameter of 300 mm, andwith the substrate and the superstrate not connected to ground. Theinitial voltage V_(i) can be estimated from the electric field strength,that is, E_(i)=10⁶ V/m, and the distance d=10 μm. This results in theinitial voltage as:

V_(i)=E_(i)d_(i)=10 V.

Using the planar capacitor approximation for the 300 μm circularelectrodes spaced by 10 μm,

C _(i)=6.25×10⁻⁸ F.

The initial electric charge Q_(i) can be obtained using equation similarto Equation (3) as:

Q _(i)=6.25×10⁻⁷ C.

Consider the situation when the electrically conductive surfaces aregrounded as shown in FIG. 6B. Using Equations (1) to (8), Q₀=6.11×10⁻⁷C; Q₁=Q₂=1.38×10⁻⁸ C; V₀=9.8 V; V₁=4.3 V; and V₂=5.5 V when the gap is10 μm. The same values will be obtained if the conductive surfaces weregrounded before the initial separation between the superstrate and thesubstrate with primordial electric charge. That charge occurs due tophysical contact of dissimilar materials. Therefore, the switches S₁ andS₂ may remain closed and ground the conductive surfaces at all times.Alternatively, the conductive surfaces may be ground at all times simplyby connecting the ground with conductive wires. For a typicalsuperstrate thickness of 700 μm, diameter of 300 μm, dielectric constantof glass 3.6,C₁=3.2×10⁻⁹ F can be calculated. Similarly, with a typicalsubstrate thickness of 750 μm, diameter of 300 μm, and for exampledielectric constant of silicon about 3, C₂ is about 2.51×10⁻⁹ F.

FIGS. 12A and 12B show the result of complete lateral separation of thesuperstrate and the substrate as shown in FIG. 7B. In FIG. 12A, theincreased spatial separation of the superstrate and the substrateincreases the space between the capacitor electrodes and reduce thecapacitance C₀ until the capacitor C₀ disappears. When C₀=0, Equation(6) becomes:

$\begin{matrix}{{Q_{1} = {{Q_{i}\frac{1}{1 + \frac{C_{0}}{C_{1}} + \frac{C_{0}}{C_{2}}}} = Q_{i}}};} & (9)\end{matrix}$

and Equation (7) is modified as:

$\begin{matrix}{V_{1} = \frac{Q_{i}}{C_{1}}} & (10)\end{matrix}$

With Q_(i)=6.25×10⁻⁷ C and C₁=3.2×10⁻⁹ F, V₁=195 V, and V₂=250 Vcorresponding to Equation (7). Calculations of the electric field insideC₁ and C₂ gives E₁=2.79×10⁵ V/m and E₂=3.33×10⁵ V/m. Both of the valuesof electric fields are far from silicon and glass dielectric strengthbreakdown, and are considered safe. The separation of superstrate andthe formable material/substrate with the conductive structures groundedresults in initial low level of electric field and absence of electricfield after significant separation. FIG. 13 shows the electric fieldstrength E₀ in the space between the superstrate and the substrate, E₁inside the superstrate, and E₂ space between the top surface of thesubstrate and the substrate chuck, as a function of vertical separation.The substrate is considered a semi-insulating silicon (Si), that is,non-conductive structure. As the vertical separation reaches 700 μm, theelectric field E₁ falls to the level of 200,000 V/m.

FIG. 14 shows the electric field strengths in the space between thesuperstrate and the substrate, E₁ inside the superstrate, and E₂ insidethe space between the top surface of the substrate and the substratechuck. The substrate and the substrate chuck are considered electricallyconductive. The substrate chuck has pin area 5% and pin height of 0.1μm. As the vertical separation reaches 700 μm, E₁ falls to the level of200,000 V/m.

FIG. 15 shows a process chart for separation process of a superstrateand a substrate after a curing process has been performed. In step S1,conductive structures are placed at the backside of the superstrate andthe substrate. In step S2, the conductive structures are grounded. Instep S3, the superstrate and the substrate are separated from each otherin a vertical direction until the electric field between the superstrateand the substrate is below a predetermined value. In step S4, furtherseparation between the superstrate and the substrate is performed in alateral direction. The surface charges are then removed in step S5.

Further modifications and alternative embodiments of various aspectswill be apparent to those skilled in the art in view of thisdescription. Accordingly, this description is to be construed asillustrative only. It is to be understood that the forms shown anddescribed herein are to be taken as examples of embodiments. Elementsand materials may be substituted for those illustrated and describedherein, parts and processes may be reversed, and certain features may beutilized independently, all as would be apparent to one skilled in theart after having the benefit of this description.

1. A planarization system for forming a layer of formable material on asubstrate with a superstrate, comprising: a first conductive portion ata second side of the superstrate, wherein the superstrate having a firstside opposite to the second side, and the first side is in contact withthe formable material in a case where the superstrate is stacked withthe substrate; and a second conductive portion at a side of thesubstrate, wherein both the first conductive portion and the secondconductive portion are grounded during a separation process to separatethe superstrate from the formable material on the substrate.
 2. Theplanarization system according to claim 1, wherein the first conductiveportion including a transparent conductive layer formed on the secondside of the superstrate before an imprint process performed on theformable material.
 3. The planarization system according to claim 1,wherein the first conductive portion includes a conductive layer placedat the second side of the superstrate after a UV exposure has beenperformed on the formable material.
 4. The planarization systemaccording to claim 3, wherein the conductive layer includes a conductivesuperstrate chuck to retain the superstrate during an imprint process.5. The planarization system according to claim 1, wherein the firstconductive portion is made of chromium (Cr), tin nitride (TiN), or tinoxide (SnO₂).
 6. The planarization system according to claim 1, whereinthe first conductive portion includes a conductive layer in the form ofa film, a sheet, or a wire mesh.
 7. The planarization system accordingto claim 6, wherein the conductive layer has a thickness of about 10 nmto about 15 nm.
 8. The planarization according to claim 1, wherein thesecond conductive portion includes the substrate chuck made ofconductive material.
 9. The planarization system according to claim 8,wherein the conductive material includes silicon carbide (SiC).
 10. Theplanarization system according to claim 1, wherein the second conductiveportion includes a conductive layer formed on the substrate.
 11. Theplanarization system according to claim 1, wherein the second conductiveportion includes a conductive substrate chuck retaining the substrateduring an imprint process.
 12. A method, comprising: curing a formablematerial sandwiched between a superstrate and a substrate; separatingthe superstrate from the substrate, including: grounding a back side ofthe superstrate, wherein the back side is opposite to a front side ofthe superstrate in contact with the formable material; grounding thesubstrate; moving the superstrate away from the substrate in a verticaldirection while both the back side of the superstrate and the substrateare grounded and until an electric field between the superstrate and thecured formable material is below a predetermined value; moving thesuperstrate further away from the substrate in a lateral direction; andperforming surface discharge while moving the superstrate in the lateraldirection.
 13. A method of reducing electrostatic field during aseparation process for separating a superstrate from a substrate,comprising: introducing a first capacitor between at a back side of thesuperstrate and a ground, wherein the back side is opposite to a frontside in contact with a formable material sandwiched between thesuperstrate and the substrate; introducing a second capacitor betweenthe substrate and the ground; and connecting the ground with both thesecond capacitor and the a third capacitor to form a close loop ofelectric current comprising the first capacitor, a-the third capacitorformed between the superstrate and the formable material during aseparation process, and the second capacitor connected in series. 14.The method according to claim 13, further comprising: separating thesuperstrate from the substrate in a vertical direction in the separationprocess until the superstrate and the substrate is completely separatedand an electric field between the superstrate and the substrate isreduced to a predetermined value; and moving the superstrate in alateral direction with respect to the substrate.
 15. The methodaccording to claim 14, further comprising performing a surface dischargeprocess before moving the superstrate in the lateral direction withrespect to the substrate.
 16. The method according to claim 14, whereinthe first capacitor is introduced by providing a conductive layer at theback side of the superstrate and an electric connection between theconductive layer and the ground.
 17. The method according to claim 14,further comprising forming the conductive layer with transparentmaterial on the back side superstrate before performing an imprintprocess.
 18. The method according to claim 14, further comprisingforming the conductive layer on the back side of the superstrate after aUV exposure has been performed.
 19. The method according to claim 13,wherein the first capacitor is introduced by providing a conductivesuperstrate chuck to retain the superstrate during the separationprocess and an electric connection between the conductive superstratechuck and the ground.
 20. The method according to claim 13, wherein thesecond capacitor is introduced by providing the substrate made ofconductive material and an electric connection between the substrate andthe ground.
 21. The method according to claim 13, wherein the secondcapacitor is introduced by providing a conductive layer on the substrateand an electric connection between the conductive layer and the ground.22. The method according to claim 13, wherein the first capacitor isintroduced by providing a conductive substrate chuck to retain thesuperstrate during the separation process and an electric connectionbetween the conductive substrate chuck and the ground.
 23. A system forforming a layer of formable material on a substrate, comprising: asuperstrate chuck with a superstrate chucking surface; a substrate chuckwith a substrate chucking surface; a first conductive portion at thesuperstrate chucking surface; and a second conductive portion at thesubstrate chucking surface; wherein both the first conductive portionand the second conductive portion are grounded during a separationprocess in which the superstrate chuck and the substrate chuck aremoving away from each other.